XTFPART Manual

NAME

xtfpart - read in an .xtf file and map the design to the Xilinx chips in BOAR

SYNOPSIS

xtfpart [-n«num»] «input file»

DESCRIPTION

xtfpart reads in the XNF file generated by XNFPrep (<design>.xtf), that is normally fed to PPR. Xtfpart parses this file, binds all external signals to the appropriate chips and pins and splits the design to the Xilinx chips in BOAR.

xtfpart will output files suitable for PPR, which is used to generate the individual configuration files for the Xilinx chips. Xilbitcat is then used to concatenate the separate configurations into a single file.

The design should use the external signal names listed below. If an external signal has a name that is not found from the list, the user must provide a new, existing name before the partitioning process can continue.

If the design is for 4025PG223, the pin names U7, U8, and U15 are automatically changed into pad identifications PAD85, PAD92, and PAD125, so that PPR won't confuse them with unbonded pins 7, 8, and 15.

OPTIONS

-n

Sets the number of dataflow chips used. Default is 3.

XILINX SIGNAL NAMES

Most BOAR signal names can be used both as buses and as separate signals. The least significant bit of the bus is always 1, but when the signals are accessed separately, the starting number may change. This non-consistency is caused by the original naming and may be corrected later.

The following lists the external signal names you can use in the design. The signals are primarily listed as buses, with the individual naming as a comment.

BOAR_IODI<1:40>

Dataflow inputs, test vector memory is <21:36>.
Can be accessed as BOAR_IODI1 .. BOAR_IODI40

BOAR_IODO<1:40>

Dataflow outputs, test vector memory is <21:36>.
Can be accessed as BOAR_IODO1 .. BOAR_IODO40

PGCK<1:4>

Primary clocks.
Can be accessed as PGCK1 .. PGCK4

SGCK<1:3>

Secondary clocks.
Can be accessed as SGCK1 .. SGCK3

BOAR_TESTVEC<1:16>

Test output from the Master Xilinx.
Can be accessed as BOAR_TESTVEC00 .. BOAR_TESTVEC15

BOAR_ADD<1:18>

Address bus for the Xilinx Data Memory.
Can be accessed as BOAR_ADD00 .. BOAR_ADD17

BOAR_DATAMEM_RW

Data Memory R/W signal.

BOAR_DATAMEM_SELECT

Data Memory Chip Select signal.

BOAR_TODSP1

Serial Data to DSP1.

BOAR_FROMDSP1

Serial Data from DSP1.

BOAR_DSP1SERCLK

DSP1/2 Serial Clock.

BOAR_TODSP2

Serial Data to DSP2.

BOAR_FROMDSP2

Serial Data from DSP2.

BOAR_TOMC

Xil_periph(37) ???

BOAR_FROMMC

Xil_periph(38) ???

BOAR_MCSERCLK

Xil_periph(39) ???

BOAR_DP1RW

Dual-port RAM 1 and Processor Dual-port RAM R/W-signal.
See the processor signal conf_DP1ENA.

BOAR_DP1BUSY

Dual-port RAM 1 and Processor Dual-port RAM Busy-signal.
See the processor signal conf_DP1ENA.

BOAR_DP1CE

Dual-port RAM 1 and Processor Dual-port RAM Chip Enable.
See the processor signal conf_DP1ENA.

BOAR_DP1ADD<1:10>

Dual-port RAM 1 and Processor Dual-port RAM Address Bus.
Can be accessed as BOAR_DP1ADD00 .. BOAR_DP1ADD09
See the processor signal conf_DP1ENA.

BOAR_DP1DATA<1:16>

Dual-port RAM 1 and Processor Dual-port RAM Data Bus.
Can be accessed as BOAR_DP1DATA00 .. BOAR_DP1DATA15
See the processor signal conf_DP1ENA.

BOAR_DP2RW

Dual-port RAM 2 R/W-signal.
See the processor signal conf_DP2ENA.

BOAR_DP2BUSY

Dual-port RAM 2 Busy-signal.
See the processor signal conf_DP2ENA.

BOAR_DP2CE

Dual-port RAM 2 Chip Enable.
See the processor signal conf_DP2ENA.

BOAR_DP2ADD<1:10>

Dual-port RAM 2 Address Bus.
Can be accessed as BOAR_DP2ADD00 .. BOAR_DP2ADD09
See the processor signal conf_DP2ENA.

BOAR_DP2DATA<1:16>

Dual-port RAM 2 and Xilinx Data Memory Data Bus.
Can be accessed as BOAR_DP2DATA00 .. BOAR_DP2DATA15
See the processor signal conf_DP2ENA.

BOAR_DSP1DP_MCDP

Processor Dual-port RAM Chip Select.
See also the processor signal conf_DP1ENA.

BOAR_DSP2DP_XCDATA

Xil_contr(34) ???

BOAR_CONTR<1:3>

Connected to the processor pins TIN1, TOUT1 and TIN2
Can be accessed as BOAR_CONTR1 .. BOAR_CONTR3

BOAR_SAMPLEIN

Input sample strobe provided by the clock Xilinx.

BOAR_SAMPLEOUT

Output sample strobe provided by the clock Xilinx.

BOAR_IOC<40:71>

Signals with no special uses.
Can be accessed as BOAR_IOC40 .. BOAR_IOC71

EXAMPLES

74 albert@harakka xtfpart > xtfpart fir_boar.xtf
Reading "fir_boar.xtf"
Checking nets
Ending net checks
Checking depths
Ending depth checks
EXT BOAR_IODO33 bound to chip 3, pin P16
EXT BOAR_IODO34 bound to chip 3, pin N17
EXT BOAR_IODO<21> bound to chip 3, pin K16
EXT BOAR_IODO<22> bound to chip 3, pin K18
EXT BOAR_IODO<23> bound to chip 3, pin L18
EXT BOAR_IODO<24> bound to chip 3, pin L16
EXT BOAR_IODO<25> bound to chip 3, pin L17
EXT BOAR_IODO<26> bound to chip 3, pin M17
EXT BOAR_IODO<27> bound to chip 3, pin M18
EXT BOAR_IODO<28> bound to chip 3, pin N18
EXT BOAR_IODO<29> bound to chip 3, pin P18
EXT BOAR_IODO<30> bound to chip 3, pin N16
EXT BOAR_IODO<31> bound to chip 3, pin R18
EXT BOAR_IODO<32> bound to chip 3, pin T15
EXT BOAR_IODI34 bound to chip 1, pin N3
EXT PGCK4 bound to chip 3, pin U1
EXT BOAR_IODI<29> bound to chip 1, pin P1
EXT BOAR_IODI<25> bound to chip 1, pin L3
EXT BOAR_IODI<21> bound to chip 1, pin K2
EXT BOAR_IODI<30> bound to chip 1, pin N2
EXT BOAR_IODI<26> bound to chip 1, pin M1
EXT BOAR_IODI<27> bound to chip 1, pin M2
EXT BOAR_IODI<23> bound to chip 1, pin L1
EXT BOAR_IODI<24> bound to chip 1, pin L2
EXT BOAR_IODI<32> bound to chip 1, pin T1
EXT BOAR_IODI<22> bound to chip 1, pin K1
EXT BOAR_IODI<28> bound to chip 1, pin N1
EXT BOAR_IODI<31> bound to chip 1, pin R1
EXT BOAR_IODI33 bound to chip 1, pin P2
SYMs: m 2 x1 29 x2 2 x3 1769
1802 of 1802 SYMs partitioned
Different types of SYM's used:
CY4        120
FMAP       177
XOR        348
AND        98
XNOR       43
OR         225
NAND       461
NOR        60
OBUF       14
IBUF       14
DFF        192
STARTUP    4
BUFGP      1
75 albert@harakka xtfpart > 

BUGS

Does not currently really do any partitioning, but puts all symbols to the last Xilinx chip. However, it DOES route all signals correctly and is thus very usable already.